Intel warns multicore chips pose programming challenge

Multicore chips will help meet growing computing demands, but it could create more challenges for programmers writing code, according to a senior Intel executive.

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Multicore chips will help meet growing computing demands, but it could create more challenges for programmers writing code, according to a senior Intel executive.

As technology develops at a fast rate, a challenge for developers is to adapt to programming for multicore systems, said Doug Davis, vice president of the digital enterprise group at Intel, during a speech at the Multicore Expo in Santa Clara, California.

Programmers will have to transition from programming for single-core processors to multiple cores, while future-proofing the code to keep up-to-date in case additional cores are added to a computing system.

Programming models can be designed that take advantage of hyperthreading, which enables parallel processing capabilities of multiple cores to boost application performance in a cost-effective way, Davis said. Intel is working with universities and funding programs that will train programmers to develop applications that solve those problems, Davis said.

Intel, along with Microsoft, has donated $20 million to the University of California at Berkeley and the University of Illinois at Champaign-Urbana, to train students and conduct research on multicore programming and parallel computing. The centers will tackle the challenges of programming for multicore processors to carry out more than one set of program instructions at a time, a scenario known as parallel computing.

Adapting legacy applications to take advantage of multicore processing is also a challenge coders face, Davis said. Writing code from scratch is the ideal option, but it can be expensive. "The world we live in today has millions of lines of legacy code ... how do we take legacy of software and take advantage of legacy technology?" Coders could need to deliver what's best for their system, Davis said.

Every major processor architecture has undergone quick changes because of the rapid rate of change as described by Moore's Law, which calls for better application and processor performance every two years, but now the challenge is to deliver performance within a defined power envelope. Power consumption is driving multicore chip development, and programmers need to write code that works within that power envelope, Davis said.

Adding cores to a chip to boost performance is a better power-saving option than cranking up clock frequency of a single-core processor, Davis said. Adding cores increases performance, but cuts down on power consumption.