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Voice System Clocking
The Cisco Integrated Services Routers offer a variety of mechanisms for implementing and
distributing clocking when connecting to external interfaces. This paper describes the clock
accuracies delivered by service providers, clocking methods available within the Cisco Integrated
Services Routers and considerations for deployments.
Networks operated by service providers, such as PSTN or WAN providers, typically act as the
clock source to any customer premises equipment (CPE) platforms connected to these networks.
The service provider edge equipment, in turn, derives its timing from a primary reference source
(PRS) such as a stratum 1 clock or global positioning satellite (GPS) signal elsewhere in the
network. Stratum levels define the allowable maximum frequency variance from the actual
reference clock, and therefore the accuracy of the clock compared to coordinated universal time
(UTC). Stratum clock types and their free run accuracy data are shown in Table 1.
Stratum Clock Types and Free Run Accuracy
Free Run Accuracy
+/- 1 x 10
+/- 1.6 x 10
(+/- 0.025Hz at 1.544MHz)
+/- 4.6 x 10
(+/- 7.1Hz at 1.544MHz)
+/- 32 x 10
(+/- 50Hz at 1.544MHz)
Specifications such as Telcordia GR-1244-CORE describe in more detail stratum-level clocking
performance criteria and specifications.
A CPE platform connected simultaneously to more than one service provider network via two or
more separate trunks (e.g., one or more PSTN, one or more WAN) results in two or more different
clock sources entering the CPE system. The variance in frequency of these two or more clocks
from one another depends on the accuracy (stratum level) of the clock provided on each trunk. If
both are stratum 1 level clocks, clock slips between the two ports will be rare. As the stratum level
of the clocks decrease (higher stratum number), the potential for clock slips increases.
Effects of Clock Slips and Corrections
Clock slip corrections on CPE system trunks affect traffic handling in different ways. A clock slip on
a TDM port carrying voice calls to the PSTN is likely to be inaudible or may cause a slight blip in
the speech path. The effect on a fax or modem may be more visible, as the fax/modem may
retrain, or the call setup may fail and retry. A clock slip on an ATM interface may cause a cell,
frame, or packet loss, and depending on the buffering algorithm and protocol retransmission logic,
is unlikely to adversely affect the end-user traffic stream.
Preventing clock slips requires that TDM traffic operate within a synchronized timing environment.
This includes all the elements involved in manipulating TDM traffic, including T1/E1 port controllers,
digital signal processors (DSPs), and other components providing supporting functions to TDM traffic
in addition to the bus or backplane of the system connecting the elements. After TDM traffic has been
packetized into IP traffic, clocking considerations are generally decoupled from traffic forwarding.