including the bonding-wires effect, using
a four-port network analyzer and micro-
probes. As Figure 10 shows, we mea-
sured the previous design s insertion loss
above 10 dB at 30 GHz. A resonance
occurs even at around 23 GHz, where the
insertion loss increases up to 15 dB.
However, the proposed design s inser-
tion loss is below 3.5 dB at up to 30 GHz,
and the 3-dB frequency is higher than
20 GHz. Furthermore, there is no reso-
nance, meaning the signal does not feel
any severe discontinuity when passing
through the package. The proposed
design shows remarkably enhanced per-
formance over the previous design.
BY AVOIDING the use of low-loss dielec-
tric material or advanced packaging tech-
nology, our WB-PBGA package can provide a low-cost
packaging solution for future high-speed serial links.
Although our consideration in this article is limited to WB-
PBGA packages, we could readily apply the proposed
design methodologies to advanced packaging technolo-
gies, further improving channel bandwidth.
References
1. W. Dally and J. Poulton, Digital Systems Engineering,
Cambridge Univ. Press, 1998.
2. H. Hofstee, Future Microprocessors and Off-Chip SOP
Interconnect, IEEE Trans. Advanced Packaging, vol.
27, no. 2, 2004, pp. 301-303.
3. C. Yang and M. Horowitz, A 0.8- m CMOS 2.5-Gbps
Oversampling Receiver and Transmitter for Serial Links,
IEEE J. Solid-State Circuits, vol. 31, no. 12, 1996, pp.
2015-2023.
4. J. Kim et al., Circuit Techniques for a 40-Gbps Trans-
mitter in 0.13- m CMOS, Proc. IEEE Int l Solid-State
Circuits Conf. (ISSCC 05), 2005, pp. 150-151.
5. X. Zhou and N. Fang, Performance of Low-Cost PBGA
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Meeting on Electrical Performance of Electronic Packag-
ing (EPEP 02), IEEE Press, 2002, pp. 71-74.
6. R. Emigh, Electrical Design for High Data Rate Signals
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218
IEEE Design & Test of Computers
0
5
10
15
20
25
30
35
40
15
10
5
0
(a)
(b)
(c)
Frequency (GHz)
Previous design
Proposed design
Proposed design with BT-MG
3 dB
Figure 8. Post-layout simulation results (a) for previous (b) and proposed
(c) designs.
(a)
(b)
GND
X2
VDD
X4
Figure 9. Photographs of assembled package and board (die
is not shown): previous design (a), and proposed design (b).
0
5
10
15
20
25
30
15
10
5
0
Frequency (GHz)
Proposed design
Previous design
Figure 10. Comparison of measured results for overall
channel performance.
